A data processing system typically comprises a host computer connected to one or more nodes, e.g., other host computers or peripheral devices, via an interconnect medium. The host computer comprises a number of basic elements including a central processing unit (CPU), a host memory and an input/output (I/O) port adapter that physically connects the computer to the interconnect medium. In general, the interconnect medium is a network or I/O bus, and the peripheral devices are typically disks, tapes and communications equipment.
The computer is functionally organized by an operating system comprising a collection of software modules that control the execution of computer programs and manage the transfer of information among the elements of the computer. The host memory stores computer program information, i.e., data and instructions, in addressable storage locations. The CPU then executes the programs by fetching and interpreting the instructions, and processing the data in accordance with the instructions.
Program-generated addresses are called virtual addresses because they refer to the contiguous logical, i.e., virtual, address space referenced by a computer program. In contrast, the physical address space consists of the actual locations where information is stored in host memory. A host computer with a "virtual" memory allows programs to address more memory than is physically available. In addition, an advantage of virtual addressing is that the addresses of the program appear contiguous even though they may reference non-contiguous physical locations in host memory. This facilitates dynamic allocation of additional addresses, as needed.
The operating system manages the virtual memory so that the program operates as if it is loaded into contiguous physical locations. A common process for managing virtual memory is to divide the program and host memory into equal-sized blocks or pages so that each program page fits into a memory page. A system disk participates in the implementation of virtual memory by storing pages of the program not currently in host memory. The loading of pages from the disk to host memory is managed by the operating system.
When a program references an address in virtual memory, the CPU calculates the corresponding host memory physical address in order to access the information (hereinafter referred to generally as data). The CPU typically includes memory management hardware to hasten the translation of the virtual address to a physical address. Specifically, for each program there is a page table containing a list of mapping entries, i.e., page table entries (PTEs), which, in turn, contain the physical address of each page of the program and a valid bit denoting whether the PTE is valid. Each PTE thus indicates whether the program page is in host memory. If not, the PTE typically specifies where to find a copy of the page on the disk. The CPU performs this virtual-to-physical address translation via specialized hardware which is not generally accessed by software.
The operating system includes at least one port driver that controls at least one I/O port adapter when performing I/O operations, such as the transfer of data between the host computer and a node. In order to efficiently perform these operations, the port driver and port adapter exchange messages, e.g., commands and responses. Specifically, the driver sends a command to the port adapter to perform an operation. The port adapter interprets the command and forwards it to the appropriate node of the medium. The port adapter then returns a response to the driver.
Typically, the commands and responses are exchanged via linked queues, which are locations in host memory organized to provide data structures. A linked queue and its associated entries are assigned virtual addresses within the virtual address space of a program. This is convenient for the port driver because the CPU performs virtual address translations within its normal program execution. However, the port adapter may be required to perform similar translations in order to locate entries in the queue in host memory. This forces the adapter to participate in the memory management process by frequently accessing host memory to reference the program page table, resulting in an increase in the time required to process a message received from the port driver. Alternately, the driver, as executed by the CPU, may translate the virtual addresses to physical addresses for the port adapter. Yet, such frequent address translation activity creates additional overhead and complexity for the driver because it does not directly access the specialized CPU translation hardware; instead, the driver must perform a more laborious software procedure. Furthermore, when processing messages received from the port adapter, the driver must translate physical addresses back to virtual addresses. This latter procedure is an extremely difficult process involving searching all PTEs for a matching physical address.
To reduce the overhead burdens, the port adapter may maintain a small, high-speed memory, i.e., a translation buffer (TB), that stores virtual address translations of recently accessed queue entries. Yet, the entries of a linked queue or other communication data structure tend to be scattered throughout virtual address space. As a result, references to the TB frequently miss, i.e., the translations of requested virtual addresses are not contained within the TB. As before, the port adapter must directly access the page table to translate the virtual addresses.
Therefore, it is among the objects of the invention to provide a communication interface between entities, such as a port driver and an port adapter, of a computer that allows independent addressing of the interface by the entities.
Another object of the invention is to provide a dual addressing arrangement for a communication queue that eliminates the need for one entity to repeatedly translate addresses for the other entity.
Yet another object of the present invention is to provide a dual addressing arrangement for a communication queue that reduces the number of accesses to host memory by the port adapter in order to locate addressing information.